1. Field of the Invention
The invention relates generally to design of integrated circuits and, more specifically, to a flow and methodology to find thermal design point power efficiency.
2. Description of the Related Art
Clock gating is one technique used to reduce an integrated circuit's power consumption requirements. The clock gating percentage is a metric commonly used to evaluate the relative thermal design point (TDP) power efficiencies for integrated circuit designs. One approach for calculating clock gating percentage is to count the number of clock gated flip-flops and compare it to the total number of flip-flops. Another approach for calculating clock gating percentage is to evaluate register transfer level (RTL) code to identify the usage of enable signals.
One drawback to measuring TDP power efficiency using clock gating percentage is that this value does not distinguish between efficient and inefficient clock gating designs. For example, a pipelined processor that has separate clock enable signals for each individual stage of the execution pipeline may be more efficient than a pipelined processor where a single clock enable signal is shared among all stages of the execution pipeline, even though the clock gating percentages for both execution pipelines are one hundred percent.
As the foregoing illustrates, what is needed in the art is an improved method for measuring the thermal design point power efficiency of integrated circuit designs.